1. Field of the Invention
The present invention relates to a read-only memory which has a multiplicity of memory cells whose contents can be read out with appropriate addressing by word, bit and source lines. The memory cells which can be addressed via an individual word line are divided into a multiplicity of groups, to each of which a separate common source line is assigned. The bit lines of different groups of memory cells are connected via connecting devices with common data output lines for outputting the data stored in the memory cells from the read-only memory.
Read-only memories (ROM, PROM, EPROM, EEPROM and the like) and methods for addressing the same are well known in the art. A practical example of the structure and addressing of a conventional read-only memory are explained below.
A typical ROM has a multiplicity of memory cells whose contents can be read out with corresponding addressing by word, bit and source lines. In the case of a ROM, in contrast to some other types of read-only memories (for example EPROM and EEPROM), the memory cells have a structure which depends on the information (“0” or “1”) to be provided during the read-out. In one embodiment of the ROM, a transistor is used, and, in a second embodiment, the transistor is omitted without a replacement and the signal lines (word, bit and source line) which are otherwise connected to the transistor run free.
However, in these prior art devices, the current consumption during reading is relatively high and reading takes a relatively long time.